The invention relates to an electronic circuit having a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The invention relates in particular to an SRAM. The invention further relates to a method of testing such a circuit.
Systematic and automatic testing of electronic circuitry, and of integrated circuits in particular, becomes increasingly more important. Each next generation of circuits tends to develop ever higher component densities and an ever growing number of system functionalities. Individual circuits have become complicated to such an extent that process defects cannot be detected and located anymore save by exhaustive and expensive testing. Customers cannot be expected to accept circuitry products that show their hidden defects in operational use, thereby rendering, e.g., life support systems or aircraft control systems, unreliable. It is therefore of the utmost importance for both the manufacturer and the customer that tests are run to guarantee flawless operation of the circuit products.
Random access memories (SRAMs, DRAMs) are usually subjected to march tests and/or data retention tests. In a march test, a sequence of read and/or write operations is applied to every cell of the memory, either in increasing or decreasing address order. In data retention tests, every cell is written and checked after a pre-specified wait-time to see whether or not current leakage has occurred that has affected the stored logic state. Note that memory cells in a bit-oriented memory and groups of memory cells in a word-oriented memory are accessible only one after the other, thus giving rise to lengthy test procedures.
Conventional testing of semiconductor memories that have a storage capacity in the order of 1 Mbit or larger makes up a considerable percentage of the production costs. With increasing transistor densities and with increasing number of system functionalities that are integrated on a semiconductor substrate (including wafer scale devices), testing has become a major factor in determining the commercial viability of an IC memory product. For further information, see "A New Testing Acceleration Chip for Low-Cost Memory Tests", M. lnoue et at., IEEE Design & Test of Computers, March 1993, pp. 15-19.
Quiescent-current testing (I.sub.DDQ -testing), also referred to as current supply monitoring method (CSM), of an integrated circuit aims at locating process defects by monitoring the steady-state currents. The I.sub.DDQ -testing technique has shown a lot of promise in the analysis of actual process defects in static CMOS ICs. The quiescent current, or steady-state current, in a CMOS logic circuit should be very small, e.g., in the order of 1 .mu.A. Any deviation is therefore easily detected. The potential of this testing technique is substantial in terms of cost reduction, and of quality and reliability enhancement.
Typical examples of defects occurring in ICs are stuck-at faults and gate-oxide defects. Stuck-at faults are symptoms caused by unintended electrically conductive interconnections between circuit nodes and supply lines, thereby effecting a hard-wired pull-up or pull-down that interferes with the circuit's logic operation. A bridging fault formed by a conductive bridge of low resistance between a supply line and a signal line causes stuck-at phenomena. Impact of gate-oxide defects is often parametric in nature, i.e., not defined in terms of logic voltage levels, and is therefore not detected by conventional voltage methods. Gate-oxide defects may also give rise to stuck-at behaviour. Typically, I.sub.DDQ -testing detects such faults.